Nagesh
My blogs
Blogs I follow
| Gender | Male |
|---|---|
| Industry | Engineering |
| Location | Bengaluru/Bangalore, Karnataka, India |
| Introduction | • Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog. • Expertise with TLM, OVM, UVM verification environment. • Good understanding of the ASIC and FPGA design flow and Digital Design. • Expertise in RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. Verification Methodologies: Coverage Driven Verification, Assertion Based Verification, Transaction Based Verification, Constrained Random Verification |