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manojob
On Blogger since: May 2012
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My blogs
Implementation of Area-Efficient Weighted Modulo 2^n+1 Adder
A TWO-CYCLE LOCK-IN TIME ADPLL DESIGN BASED ON A FREQUENCY ESTIMATION ALGORITHM
A POWER EFFICIENT TWIN PRECISION TECHNIQUE FOR MULTIPLIER DESIGN
Design of High Speed Reconfigurable FFT (Fast Fourier Transform)
Multi valued logic
Low power and high performance 4-bit register using conditional discharge flip flop
New Architectural Design of Cellular Automata Based Codec
FPGA DESIGN OF BINARY PHASE SHIFT KEYING AND QUADRATURE PHASE SHIFT KEYING MODULATOR AND DEMODULATOR
About me
