Delete comment from: Ken Shirriff's blog
Does anyone know why the pullup transistors are so big? I know that they need to have a big L/W ratio compared to the pulldown to give a good voltage transfer curve. (Though the NOR gate seems to have W_pulldown/L_pulldown/(W_pullup/L_pullup) = approx 6.5 which is a bit higher than the factor 4 derived in Mead & Conway - I wonder why?)
But what strikes me even more in this case is that all the pullups seem to have a width that is more than twice the minimum gate length, and they take up a lot of space on the die. Couldn't they have shrunk the pullups by a factor of 2 or at least 1.5 in both length and width, and saved a lot of space on the die?
I wonder if the pullups are actually using the minimum gate width, just that that is much bigger than the minimum gate length? They're not much wider than the pulldowns at least.
Or if it has something to do with that the pullups seem to be using buried contacts to connect the poly to the diffusion, where the buried contact is touching the pullup itself? Many other chips (6502, Z80 at least) seem to prefer to have the buried contact a little distance away, to improve manufacturing tolerances perhaps?
Jan 22, 2021, 1:22:49 AM
Posted to Silicon reverse engineering: The 8085's undocumented flags