Delete comment from: Ken Shirriff's blog
Awesome teardown. "In the photo, the EEPROM appears to be a 64×64 grid, 4K bits of storage rather than the advertised 1312 bits." Due to processing variations (especially with CMP) the cells at the edge of a memory array often behave a little differently than the ones in a more consistent environment. So designers often add a few dummy rows and columns on all sides to make the main array consistent. There are also probably some redundancy sectors or other sectors that are physically there, but not visible to the end user.
Jun 23, 2024, 6:26:30 PM
Posted to Inside the tiny chip that powers Montreal subway tickets