Delete comment from: Ken Shirriff's blog
Another great article! However:
> The idea is that when the first clock is high...
I'm not sure about this bit. We sometimes used to call the two clocks capture and relaease. When the release clock rises, the new value starts to propagate towards the receiving latch. When the capture clock falls, the final value from the logic is frozen. The evaluation time is from the rise of one clock to the fall of the other. The non-overlap time is dead time, and also is the safety margin for clock skew. Notably, it's possible to use the two clocks in either sense, in different places for different purposes, which can, for example, help to provide stable control signals for a datapath. See the 6502.
Aug 15, 2020, 3:16:03 PM
Posted to How the 8086 processor handles power and clock internally